1. Field of the Invention
The present invention relates to a semiconductor memory. More specifically, it relates to a semiconductor memory that relaxes intervals between bit lines (BL), and prevents defects of a bit line (BL) and a via contact (VIA) due to the bit line and the via contact being very closely disposed, and a fabrication method for the same.
2. Description of the Related Art
In order to implement a large capacity, low cost NAND flash EEPROM, miniaturization of device dimensions and the like, based on a scaling law, is essential. However, because advanced design rules for miniaturization continue to be developed and processing precision becomes more strict as miniaturization progresses, process technologies for implementing a miniaturized NAND flash EEPROM cannot keep pace.
The structure of a NAND flash EEPROM can be substantially divided into a cell array region and a peripheral circuit region. Less strict design rules than those for the cell array region are applied to the peripheral circuit region because processing precision for the peripheral circuit region needs to satisfy desired transistor performance specifications such as electric current and withstand voltage. On the contrary, miniaturization is always being pursued to the limit of process technology because high performance of memory cell transistors that constitute the cell array region is not strongly demanded and a uniform arranged layout is possible.
With the cell array of a conventional NAND flash EEPROM, (1) active regions (AA) and element isolation regions, (2) gate electrodes (CG), (3) bit line contacts (CB), and (4) bit lines (BL) may have minimum fabrication dimensions. Leading-edge, costly apparatus and materials must be adopted in order to implement the above-mentioned processing precision with minimum fabrication dimensions. Accordingly, the more areas with the minimum fabrication dimension, the more the cost increases, resulting in a loss of product competitiveness.
The pitch of particularly bit lines (BL) is the same as that of the active regions (AA) or the element isolating regions (STI), and width of the bit lines (BL) is the same as that of the active regions (AA) or the element isolating regions (STI) when using the conventional interconnecting method. Since ensuring resistivity and maintaining sheet resistance to a degree that does not allow delay are necessary regardless of whether the interconnects become narrower due to miniaturization, interconnect layer thickness is increased and processing difficulty is typically increased due to a scaling law when the same interconnect material is used.
In addition, defects of a bit line (BL) and a via contact (VIA) due to the bit line and the via contact being very closely disposed have recently become more and more evident.
While a NAND flash EEPROM has been taken as an exemplary nonvolatile semiconductor memory thus far, the same issues holds true for other memory operating methods. For example, NOR, DINOR, AND, and AG-AND type memories, which have assist gates adjacent to floating gates, are typical nonvolatile semiconductor memories other than a NAND flash EEPROM (for example, see, Y. Sasago, et. al, “10-MB/s Multi-Level Programming of Gb-Scale Flash Memory Enabled by New AG-AND Cell Technology”, Technical Digests of International Electron Devices Meeting, 2002 IEEE, 21.6.1, p. 952-954). These structures share a common problem, i.e., in order to connect memory transistors or select gate transistors to bit lines, there are areas in which bit lines and via contacts are densely aligned.
A NAND EEPROM having a two-dimensional device pattern with twisted bit line electrodes so that coupling noise, which is generated between adjacent bit lines, can be reduced through bit line shielding technology has already been proposed (for example, see Japanese Patent Application Laid-open No. 2003-204001 (FIG. 2)).